| ||
Santa Cruz, Calif. - Seeking to write the book on how to use SystemVerilog for verification, Synopsys Inc. and ARM Ltd. are working together on a SystemVerilog Verification Methodology Manual and hope to have it ready by June.
The book-which is being written by several noted verification experts-will offer a reference methodology for coverage-driven verification using SystemVerilog. It promises to provide engineers with guidelines and industry "best practices" for system-on-chip design and to give intellectual-property developers a standard architecture for building interoperable verification IP.
"One thing we've heard from customers is that the [SystemVerilog] technology is really valuable, but they'd like to have access to a clear methodology they can use to benefit from these powerful constructs," said Swami Venkat, director of marketing for RTL verification at Synopsys. "That's why we decided to collaborate on this methodology."
ARM signed on to the project after observing the rapid acceptance of SystemVerilog, said Tim Holden, ARM's strategic worldwide EDA vendor relations manager. "Some of our major licensees told us they'd be doing their next ARM project using SystemVerilog. What we'd like to do is to have a methodology where we can provide IP and verification files, so it can be used by just about anyone in the world regardless of tool sets."
Both Venkat and Holden said that the book will not describe tools from their respective companies, but will be valuable to engineers regardless of their choice of EDA vendors or IP providers. The concept follows in the footsteps of the Reuse Methodology Manual, published in 1998 and co-authored by technologists from Synopsys and Mentor Graphics Corp.
Authors of the Verification Methodology Manual (VMM) include Janick Bergeron, moderator of the Verification Guild Web site and an R&D engineer with Synopsys; Phil Moorby, creator of the Verilog language and a Synopsys scientist; Peter Flake, a Synopsys scientist; John Goodenough, worldwide design methodology manager at ARM; Andrew Nightingale, SoC verification manager for ARM; and Alan Hunter, verification methodology manager for ARM.
The draft is still in progress and the companies haven't chosen a publisher, Venkat said. But he offered a preview.
Venkat said the VMM will explain SystemVerilog verification constructs and show how to use them. It will define an architecture that an engineer can use to put together a verification environment, including constrained-random-generation techniques, functional-coverage analysis, and both dynamic and formal verification. It will also talk about SystemVerilog constructs for transaction-level verification with SystemC.
The book will describe how to use assertions in both dynamic and formal verification. It will provide "building blocks" for testbenches, including such components as stimulus generation and error logging, Venkat said.
The VMM will also include a spec for a standard set of libraries for assertions and for commonly used verification functions. Synopsys will ship these libraries with its Discovery verification platform, but the specification is open to all, Venkat said. "Any verification environment put together using these guidelines will become VMM-compliant," he said.
"When ARM delivers IP, we can deliver verification files that comply with this methodology," Holden said. "Hopefully this methodology will be adopted by more and more users. Then, when we deliver IP, we'll only have to package it in one particular way, and the verification files only have to be written once."
Venkat said the VMM will cover the existing SystemVerilog 3.1 specification and may include the upcoming 3.1a spec, depending on when it comes out. The book is expected to be available at the Design Automation Conference June 7 to 11 in San Diego.