Implementing nanometer-scale ICs begins and ends with wires. Wires are so dominant that little is known about a design's performance or manufacturability without them. In fact, nanometer design strategies that are not clearly focused on rapid wire creation, optimization, and analysis are destined to fail.

This paper describes the requirements for an effective, reliable IC implementation platform for the 90 nm process node and beyond. It begins with a description of the central role wires play in nanometer design and why traditional linear design flows are insufficient. It then describes a new continuous convergence methodology, which has proven highly valuable at 0.13 micron and will be absolutely necessary at 90 nm.

Next, the paper describes the key implementation, analysis, and database technologies needed to enable this methodology. Implementing nanometer designs requires nanometer routers that optimize wire creation for both performance and manufacturability. Verifying nanometer designs requires nanometer analysis tools that accurately model physical effects as they would occur in the target silicon. Efficiently representing these designs-most of which will be large digital designs with critical analog circuitry-requires unified nanometer databases with massive capacity and efficient extensibility.

Wires must be the centerpiece of any nanometer methodology. Without such a methodology, design teams will not be able to create massively complex nanometer ICs in a timeframe of relevance.

2 Wiring dominates nanometer design

In nanometer design, wiring delay accounts for the vast majority of overall delay. It is well known that delay has been shifting from gates to wires for quite some time. As shown in Figure 1, wiring delay exceeds gate delay at 0.18 micron and below in aluminum processes, and at 0.13 micron and below in copper. By 90 nm, wiring delay will account for some 75% of the overall delay. As a result, design teams need to shift their focus from logic optimization to wire optimization.

Figure 1: Wire and gate delay in Al and Cu

2.1 The changing nature of delay
In addition to dominating overall delay, nanometer design exacerbates physical effects that introduce substantial delay-notably signal integrity (SI) and IR (voltage) drop. These effects can be considerable even at 0.18 micron. By 0.13 micron, "sign-off" timing analysis tools miss numerous SI- and IR drop-based degradations that are comparable in magnitude to the nominal timing and much more difficult to predict. Yet, many design teams continue to use delay calculations based on over-simplified models (such as lumped capacitance) down to 0.13 micron. Doing so results in both reduced performance-due to high margins-and excessive, time-consuming design iterations. At 90 nm, timing analysis that does not include SI and IR drop effects is essentially meaningless.

2.1.1 Cross coupling
Delay is a function of wire loading and wire drive. At 0.25 micron and above, the primary wire capacitance is due to coupling to electrical ground and is largely proportionate to wire length; doubling the wire length doubles the capacitance. Steiner, or global, routing estimates predict the wire length based on placement.

As process geometries decrease, the primary capacitive coupling on a given wire moves to its neighboring wires. Capacitance depends on the local wire geometry and, in many cases, to the actual signals on neighboring wires. As an example, Figure 2 shows delay variation at 0.18 micron due to capacitive coupling for signals at 1X and 2X grid spacings. The variation is up to +/-30% for 1 mm wires and +80%/-60% for 3 mm wires.

Figure 2: Crosstalk introduces substantial delay variation

At 0.18 micron, cross coupling affects only high-performance designs significantly. By 90 nm, it will significantly affect all designs. Since capacitance is no longer strictly proportional to wire length at nanometer geometries, detailed routing is required for accurate timing analysis.

2.1.2 IR drop
Resistance in the power and ground wire networks creates IR drop. Nanometer designs are extremely susceptible to these effects because this resistance increases with decreasing feature sizes. It is further exacerbated when the overall power supply voltage decreases because this also decreases the usable region of the signal transitions. With decreasing supply voltage, gate delays and noise susceptibility increase. An IR drop from 1.7V to 1.6V is capable of producing delay variations of 50% or more. One study of designs at 0.18 micron and below showed that 20% of designs failed on first silicon due to excessive IR drop alone.

2.2 Nanometer technical issues
Nanometer design, in fact, exacerbates a host of technical issues that exist at 0.13 micron and above. It also introduces new technical issues related to complexity, physical effects, and manufacturability. Table 1 lists some of the most important nanometer design issues. A brief description of each appears in the Appendix.

Table 1 -- Critical nanometer design issues

The most striking feature of any list of critical nanometer design issues is the number of issues that relate to wiring. At nanometer geometries, wiring dominates nearly all aspects of IC implementation-including design time, performance, area, and manufacturability.

3 Continuous convergence methodology

The critical role wires play at the 90 nm process node and beyond makes traditional linear design flows ineffective. Nanometer design requires a completely different design strategy-continuous convergence.

3.1 The need for a design strategy
Traditional IC implementation approaches are linear in that designs move sequentially through a series of stages-RTL, gates, power planning, placement, clock tree design, routing, and physical analysis. When gates dominate delay, this process is predictable and efficient because performance optimization and analysis iterations occur early in the flow.

As the percentage of delay in the wires increases, linear flows become more unpredictable and inefficient. At 0.18 micron, performance is unknown prior to placement. Using floorplanning and physical synthesis tools, designers can iterate at the placement level to try to find a feasible solution (see Figure 3). When there is no feasible solution, they must go all the way back to change the architecture or logic. The high probability of long iterations greatly reduces predictability, while the iterations themselves greatly reduce efficiency. At 90 nm, performance is unknown prior to detailed routing; this introduces more iterations and longer iterations-and much less predictability and efficiency.

Figure 3: Optimization and analysis iterations by process node

With timing based primarily on wires in nanometer designs, design teams must use methodologies that both generate wires as soon as possible ("time-to-wire") and minimize full-chip iteration time. Time-to-wire and full-chip iteration time will be the critical metrics for design predictability and efficiency in nanometer design.

3.1 Floorplanning is insufficient
Floorplanning uses a full-chip, global physical topology and estimated physical data to produce timing and congestion analysis estimates. This information is helpful only if it is accurate, yet the only way to get accurate information at the nanometer level is by analyzing realistic wires-including physical effects such as crosstalk and IR drop. Since floorplanning information is not based on realistic wires, the result at nanometer levels will be an unpredictable, inefficient flow that produces sub-optimal designs.

3.1.2 Physical synthesis is insufficient
Physical synthesis-that is, concurrent optimization of logic and placement-provides significant advantages at 0.18 micron and 0.13 micron versus traditional wireload-based logic synthesis. Physical synthesis is based on gates, placement, and Manhattan wire estimates, which do not include capacitive coupling, metal layer, or detailed routing effects. Since each of these effects has a substantial impact on overall delay, physical synthesis simply does not have adequate information to close timing for nanometer designs.

Despite early market predictions that physical synthesis would replace logic synthesis, design teams use it only to re-optimize gate-level blocks that do not meet timing. In nanometer design, design teams will use physical synthesis only on those blocks that full-chip detailed routing identifies as not meeting timing. At that point, physical synthesis serves as a valuable optimization engine to provide routing with a better starting point for wire optimization. However, the wires themselves-not the logic or placement-will dictate performance.

3.2 Nanometer design methodology: Continuous convergence
Successful nanometer design methodologies must minimize time-to-wire and full-chip iteration time. The continuous convergence methodology meets these requirements. In fact, a substantial, and growing, number of companies have adopted continuous convergence at 0.13 micron with outstanding results versus linear flows.

3.2.1 A virtual tapeout every day
Continuous convergence begins with an initial full-chip design representation with wires, called a silicon virtual prototype (SVP). The SVP treats all aspects of the design-logic, timing, SI, power drop, electromigration (EM), I/O issues, and manufacturability-concurrently. Design teams use the SVP to identify and prioritize performance and manufacturing issues, then individual designers work on the highest priorities. When ready, the team integrates all design changes into the SVP and re-analyzes the entire design.

Design teams that use continuous convergence often standardize on a one-day turnaround-in essence, performing a virtual tapeout every day. Thus, every day they see predictable, measurable, systematic progress toward their goal of silicon closure and final tapeout (see Figure 4).

Figure 4: Continuous convergence methodology

3.2.2 Silicon virtual prototype
The SVP is key to the continuous convergence methodology. An SVP must be a complete full-chip implementation that is close enough to tapeout quality where designers can accurately assess all relevant aspects of the design. Yet, it must execute fast enough that designers can iterate rapidly in order to try different implementation directions. A prototype without detailed wiring may help guide logic design, but it will not guide nanometer physical design adequately.

The SVP must support clock structures, power grid, top-level interconnect, and other characteristics of the tapeout design. It must account for all relevant overhead in order to represent a known, physically feasible solution which can guide decisions such as timing-budget and pin assignments-a fully detailed layout with wiring is the only way to guarantee feasible budgets and assignments.

Figure 5: An SVP can serve as a design cockpit

An SVP can serve as a universal cockpit for all tools and functions, combining all aspects of implementation and analysis within a single full-chip environment (see Figure 5). This environment can include implementation functions-floorplanning, placement, physical synthesis, routing, clock-tree synthesis, and power planning-and analysis functions-timing, signal integrity, routability, and power analysis.

3.3 Hierarchical and high-capacity flat support
Most nanometer designs will be enormous by today's standards. In fact, designs containing over 1 billion objects are already being developed at 0.13 micron. At 90 nm, designs with less than 10M gates will be considered small, and many design teams will want to create them flat. Of course design teams will need to use hierarchy for large designs, yet even in these cases, very high capacity is necessary to minimize the amount of hierarchy needed.

Continuous convergence must support hierarchical and high-capacity flat designs. Tool capacity is critical in either case. Nanometer tools will need massive capacity and performance compared to today's standards. Many current IC implementation tools have practical capacities on the order of 1M gates. Yet some tools have a much less useful capacity, requiring otherwise unnecessary hierarchy. This hierarchy can introduce substantial overhead, such as the need for budgets and constraints, and reduce overall optimization opportunities. It also adds risk-a single incorrect time-budget value can make an otherwise feasible design impossible.

Obviously, tools should not constrain designers unnecessarily. All nanometer tools should have the capacity and performance to handle 10M gate designs flat, an order-of-magnitude increase over today's nominal capabilities. This is achievable through a number of means including improved algorithms and data structures, and using multiple processors. A 10M gate useful capacity provides design teams with much more freedom to choose when and how to utilize hierarchy.

4 Nanometer routing requirements

Full-chip detailed routing is the first step in assessing a design's initial performance. It is also the last step in optimizing the design to meet all of its performance and manufacturing requirements. Nanometer design demands a new type of router that is physics-aware, manufacturing-aware, and has massive capacity and performance.

4.1 Physics-aware routing
Above 0.13 micron, only teams with very high-performance designs need to deal with adverse physical effects. Doing so requires extremely expensive manual approaches. By 90 nm, the number and difficulty of problems will increase to the point that it will be completely impractical for most design teams to correct them manually. Instead, design teams will need routers that address physics effects-beginning with SI and IR drop-on-the-fly in order to close timing.

4.2 Manufacturing-aware routing
For the most part teams have focused exclusively on timing closure, confident that the result would be manufacturable. Above 0.13 micron, manufacturing procedures such as optical proximity correction (OPC) were performed after generating the fully routed, and otherwise correct, GDSII. Design teams could also ignore the effects of physical manufacturing processes.

Most design teams run into manufacturability issues for the first time at 0.13 micron. Processes using copper wiring, chemical-mechanical polishing (CMP), and subwavelength lithography lead to exceedingly complex and arcane design rules. Antenna rules, to take one example, require careful handling to avoid via proliferation and minimize wire lengths. Furthermore, foundries continue to change the design rules long after the introduction of a new process in order to optimize time-to-silicon production.

Nanometer routers must explicitly provide for variable width and variable spacing, and they must be capable of adapting to the requirements of copper, multiple vias, OPC, phase-shift masking (PSM), and CMP. Beyond 90 nm, routers will have to optimize the wiring specifically to facilitate manufacturing processes. Nanometer designs will challenge any router that is not designed specifically to account for these advanced process considerations.

4.3 Massive routing capacity and performance
At 0.13 micron and above, design teams can perform routing block-by-block, then use a chip-level router to connect the blocks together and perform tasks such as generating the top-level clock tree. Nanometer routers must be capable of working simultaneously at the block-level and chip-level.

The router must be tightly coupled with, and have control over, almost every aspect of the physical realization of the chip, including:

• Routing-optimized placement
• Local logic optimization for timing fixes and area recovery
• Clock tree construction and balancing, including useful skew
• Power grid construction based on IR drop and EM analysis

Nanometer routers must have concurrent access to full parasitic extraction, full-chip static timing analysis (STA), and signal integrity analysis, using these results to guide and to modify routes on-the-fly. High-end design teams must account for the complex interactions between signal, power, and clock routing. For instance, in 90 nm high-performance designs high-speed clock routing must be tightly controlled using techniques such as shielding, track assignment, and topology control. Routing must be integrated with automatic clock tree synthesis and clock timing analysis.

Performing the above, along with supporting variable wire widths and spacings, requires massive capacity and performance. A meaningful benchmark is the ability to route a 10M gate design overnight. Doing so is likely to require multithreading and multiprocessing in order to utilize all computational resources available for the task.

5 Nanometer physical analysis requirements

Every process node change introduces new challenges. The simultaneous move to copper at 90 nm causes more, and more difficult, problems than usual. These problems make it all the more difficult to get accurate analysis information. Successful nanometer design requires the use of nanometer-scale analysis tools throughout the design process. These tools should not only identify problems, but also provide guidance for addressing them.

5.1 What you see is not what you get
At nanometer levels, what you see in layout is not what you get in silicon. In fact, it is not even close. Wire widths change due to optical distortions from subwavelength lithography. Wire thicknesses change due to CMP on copper wires, producing effects such as erosion and dishing. Such distortions substantially affect electrical characteristics-capacitance, resistance, and inductance-and reliability-EM-in signal wires, clock, and the power grid. Design teams need analysis information that reflects these realities.

With the right analysis information, design teams can also get significantly more performance out of a given process technology. Microprocessor design teams using full-custom techniques often achieve 7x to 10x higher frequencies at given process nodes than typical ASIC design teams using semi-custom techniques. A considerable part of the difference is based on having accurate physical analysis information, which enables designers to cut margins tremendously. As a result, they can gain performance at a given process node or reduce the cost per chip by using a less expensive process node.

5.2 Parasitic extraction
Extraction accuracy is essential. Accuracy is largely a function of the relationship between the tool vendor and the foundry. Tool vendors need early access to proprietary process information to determine how best to model the process and to capture the necessary process characteristics. Accuracy is also a function of the design representation. Tools need to use the physical details of design elements, rather than simplistic abstractions. As an example, while it is expedient to provide a simplified model of a port, doing so inherently limits design optimization. Similarly, cell models should be instance-specific, not treated as if each cell were isolated.

From a methodology point of view, getting the most out of the silicon requires utilizing the most accurate physical information necessary during every design iteration. During early design iterations, turnaround time is at a premium. Later in the design cycle, accuracy is most critical. Using a less accurate extractor to speed iterations can mean increased margin and increased timing closure risk. An extractor should be fast enough to enable designers to complete block iterations within 1-2 hours. It should also complete a full-chip extraction overnight, using multiprocessor computers if necessary to do so.

5.3 Delay calculation
Delay calculations performed by today's "sign-off" timing analyzers are inaccurate. These tools often use over-simplified models (such as lumped capacitance) that do not take into consideration dynamic effects on the wires, which in turn have dynamic effects on cell delays. Cell delays change with loading on the gate as well as with coupling effects on nets. The delays are dynamic, not fixed. To be accurate, delay calculation must be based on more than a behavioral abstraction of the cell. It must take current and capacitance characteristics into consideration, down to the transistor level. Cell delay calculation based on lumped capacitance simply is not accurate enough for high-frequency circuits. Nanometer delay calculation must be based on SI and IR drop (see Figure 6).

Figure 6: Nanometer delay calculation with SI and IR drop

Hierarchical delay calculation is also important in nanometer design. Simplistic, conservative timing models at hierarchical boundaries increase margins. Delay calculations must correctly model paths that cross hierarchical boundaries to maintain accuracy.

5.4 Signal electromigration
Despite early beliefs that copper would ease all electromigration (EM) issues, the opposite might in fact be true. Aluminum's resistance to EM increases with narrow wires due to its "bamboo" structure, which is not the case with copper. In addition, tungsten vias help isolate potential EM effects to net segments, whereas copper vias used in copper processes enable potential EM effects to propagate throughout the entire net.

Signal EM becomes more of a problem as wires get smaller and designers are forced to push more current through them to meet performance. Place-and-route tools that create large drivers on nets to meet timing can create EM problems throughout a massive chip-problems that design teams do not even know about. Nanometer physical analysis must identify EM problems before they occur in silicon, including AC-induced EM due to high-frequency signals-generally those over 300 MHz and those with many hazard-as well as DC-induced EM due to large unidirectional current flow.

5.5 Power grid analysis
Power grids account for approximately two-thirds of all wires. In nanometer designs, they will contain over 1 billion wire segments (resistors). As opposed to signal nets, which are generally considered one at a time, power grids must be analyzed in their entirety, making tool capacity important and hierarchy support crucial. Power grid analysis must include IR drop and EM analysis. Using over-simplified models to accelerate IR drop analysis can be an extremely expensive shortcut when the silicon fails due to EM.

Accurate power-grid analysis requires modeling design activity that is representative of the actual signal transitions. It is getting extremely difficult to provide adequate vector sets for many complex designs. Power-grid analysis tools should be able to use probabilistic techniques which can provide accuracy that neither static methods nor vector-based methods can match for a growing number of designs. For accuracy, power-grid analysis must also take into consideration manufacturing techniques such as OPC and PSM, necessitating the ongoing model calibration to foundry silicon.

5.6 Inductance
Inductance is the next big SI issue to address. Specialized solutions focused on extraction exist today for very small circuits. While vendors are beginning to introduce specialized capabilities for larger designs, complete solutions are unlikely in the near term. One major challenge in extracting and analyzing inductance is that doing so can be extraordinarily computationally expensive, requiring perhaps an order of magnitude more computation than cross-coupling analysis for the most detailed solutions. Continuous convergence can help design teams identify the wires that are most susceptible to inductance problems, so they can utilize such computationally intensive tools beneficially.

6 Nanometer design database requirements

The right database is more important than ever in nanometer design, with its massively complex chips, elaborate physical requirements, arcane manufacturing requirements, and all that is still unknown. The majority of nanometer designs will be digital/mixed-signal ICs (i.e., large digital designs with critical analog circuitry) making it particularly important to that the database support a unified data model.

There was much debate in the early 1980s over the then-novel concept of combining geometric data and its associated connectivity data in a single database. Yet taking that step enabled some of our most significant algorithms advances including connectivity-based editing, place-and-route, physical synthesis, and efficient physical verification. The time is right for a next-generation unified database.

6.1 Unified data model
Nanometer design requires a unified data model-a single design representation that can contain all information about every aspect of design, including schematic, netlist, and layout representations; digital and analog representations; and cell-based and custom representations. It must also support all associated information for these design representations, including physical layout, logical and physical connectivity, extracted and reduced parasitics, timing constraints, and detailed manufacturing data, such as OPC and PSM.

A unified database enables all design tools to operate off of a common representation, eliminating time-consuming and error-prone file transfers. Each application can focus on only the relevant parts of the database-as developers add new data types, only those applications that need the new data need to change. With today's interchange formats, every application must understand, store, and output all information contained in the format-often resulting in information loss. A unified database eliminates such loss as each tool reads, reinterprets, transforms, and writes it.

Figure 7: Nanometer database with unified data model

A unified database allows for new algorithms that use design intent currently only accessible to specific tools. For example, an OPC creation tool can examine the slack on each signal before selecting which correction to apply, reducing mask complexity and cost. Another example includes intelligent mixed-signal design partitioning, simulation, and analysis.

6.2 Key features
A nanometer database should support advanced constructs for nanometer physics and manufacturing, such as area fill, wire slotting, OPC, and PSM. Explicit support for OPC and PSM constructs, for example, means that a single design file can include the pre-OPC/pre-PSM layout along with the OPC/PSM changes. Design teams will then be able to migrate to new manufacturing processes from the original layout more easily. Explicit constraint support ensures synchronization with the design representation, eliminating the use of incorrect constraint files. Nanometer designs will contain many different types of circuitry, including digital logic, analog, RF, memories, and programmable logic. To optimize performance and manufacturability, the database should support multiple design rule sets for a given design.

6.3 Massive database capacity and performance
Nanometer databases should provide a 10x capacity improvement over the previous generation of physical design databases without degrading performance. In fact, performance on operations such as read and write need to get significantly faster. Transparent support for 32-bit and 64-bit versions of popular processors and operating systems is also important. Most designers prefer using 32-bit machines. Transportability enables them to do so for design representations within the memory limit. Designers who need to use applications beyond the 4GB limit should be able to do so without the entire design team having to move to 64-bit machines.

High database performance enables many tools to operate directly off the database, saving application development time. While some tools will use their own proprietary data structures for runtime efficiency, the persistent repository will remain the centralized database. If the database also has an appropriate extensibility model, fewer and fewer applications will duplicate structures, such as the netlist, that already exist in the database.

6.4 Extensibility and openness
It is impossible to predict all future design information requirements, so nanometer databases should support the creation of new object types, the addition of attributes to existing objects, and the definition of new relationships among objects-all with native speed and efficiency. Such extensions must be lightweight, space-efficient, time-efficient, and optimized for the particular data type.

With appropriate extensibility, application developers-including in-house and third-party tool developer-can write efficient algorithms to manipulate and analyze the data they need precisely at full speed. Extensions should be available permanently to enable other tools to use them, or temporarily to serve as a coherent high-performance cache. In-memory coherence makes it possible to write tools built from cooperating components that are incremental in nature, to use lazy evaluation techniques, and to provide application-level toolkits that allow rapid new tool evolution and construction.

Nanometer databases should be open, which includes having an open application programming interface (API), open source code, and a community-based oversight committee. Openness is not a technical requirement per se, but it directly facilitates a technically superior implementation that advances rapidly. It also mitigates design team risk by enabling native third-party and in-house application development.

6.5 The future - connecting with manufacturing
Moving forward, nanometer databases should support direct, database-level interaction with manufacturing to enable "GDSII-less" handoffs and provide important design intent that GDSII cannot represent. Mask shops could use design intent to lower tolerances for non-electrically active portions of the design such as area fill and reducing mask creation time and expense. Foundries could use design intent to optimize their processes based on specific design characteristics, perform more effective and efficient test and analysis, and optimize yield. Foundries could provide manufacturing feedback mapped to any design representation and potentially even encapsulate their increasingly complex design rules in the database.

7 Conclusions

Wires dominate performance and manufacturability at 90 nm and below, making traditional linear flows obsolete. Wires are so important that performance analysis or optimization without detailed routing information is essentially meaningless.

Successful nanometer physical IC design requires wire-centric strategies, such as the continuous convergence methodology presented in this paper. It is a proven methodology that minimizes both time-to-wires and full-chip iteration time. Design teams that use continuous convergence see predictable, measurable, systematic progress toward their goal of silicon closure and final tapeout.

Nanometer success also requires a new set of implementation, analysis, and database technologies. Nanometer routers must be physics aware, taking physical effects such as SI into consideration on-the-fly. They must also be manufacturing-aware, with capabilities such as variable-spacing and variable-width routes to support copper, CMP, and subwavelength processes. Nanometer physical analysis must represent the target silicon accurately.

Silicon integrity and IR drop have become first-order timing effects, and EM is an issue for signals as well as the power grid. An extensible, unified database provides the foundation for nanometer design, especially since most designs will be digital/mixed-signal. It needs to support a rich set of objects, attributes, and relationships. Perhaps more importantly, it must support extensibility with native performance. The database and all nanometer tools should support hierarchy elegantly and handle 10M gate designs efficiently.

Nanometer design implementation places extraordinary demands on design teams. Those that embrace wire-centric design strategies such as continuous convergence will thrive at the expense of those that do not.

Appendix: Critical nanometer design technical issues

Below are descriptions of 10 top technical issues associated with nanometer design.

Table 1 -- Critical nanometer design issues

1 Design size and complexity
At 0.18 micron, there are designs with over 250 million transistors. Nanometer designs will support multiple-billion transistors within the next few years with no corresponding relaxation of time-to-market demands. Implementing these designs will require nine or more layers of metal, multiple metal pitches, via densities measured in millions per square centimeter, and pervasive use of flip-chip packaging to distribute thousands of I/O pins. These advances create three related issues designers must address-capacity and performance; early, accurate analysis; and hierarchy to manage complexity. A nanometer design environment must have the capacity and performance to handle these huge chips while imposing as few methodology restrictions as possible.

2 Timing based on signal integrity
As described throughout this paper, timing analysis in nanometer designs that does not include signal integrity (SI) and IR drop effects is essentially meaningless. At 0.13 micron, "sign-off" timing analysis tools fail to catch numerous SI and IR drop based degradations that are often comparable in magnitude to the nominal timing and much more difficult to predict. Timing nanometer designs accurately requires realistic wires, advanced interconnect modeling techniques, and sophisticated physical analysis.

3 IR drop (power grid design)
Resistance in the power and ground distribution network causes IR drop. Nanometer designs are extremely susceptible to IR drop because power and ground wire resistivity increases with decreasing geometries, while the overall power supply voltage decreases. Gate delays increase non-linearly as voltage at gates decrease. The result is poor performance and increased noise susceptibility. Furthermore, gates with different voltage levels communicating with each other across the chip can propagate erroneous data, causing a malfunction. The power grid must be robust enough to prevent reliability problems from EM effects without costly over-design. In nanometer design, it is essential to understand power issues early in the design cycle, and in detail, to minimize power consumption and to address considerations such as temperature, leakage, return path, etc.

4 Crosstalk and inductance
When signals in neighboring wires transition, the coupling capacitance between the wires can cause crosstalk. The amount of crosstalk depends on the mutual capacitance between the wires and the signal slew (the switching speed). Crosstalk causes noise problems when a transition on a fast aggressor wire causes a glitch to appear on a victim wire. The situation is more complex when simultaneous switching occurs on both wires. This situation can create crosstalk-induced delay changes which speed up or slow down signals depending on their phase relationship. Inductance between the wires can exacerbate crosstalk. Coupling capacitance and inductance effects increase with decreasing process geometries, which will make it important to account for these effects on crosstalk generation. Beyond 90 nm, it will become important to account for an increasing number of inductive effects, such as power rail "ringing" due to the simultaneous switching of multiple gates.

5 Electromigration
Electromigration occurs when the current per cross-sectional area in a wire or via is too high. In power and ground wires, a current-induced "electron wind" causes metal ions to migrate, creating voids "upwind" and metal-ion accumulation "downwind" in the form of "hillocks" and "whiskers." Voids can also cause open circuits or increase wire resistance, which in turn increases delays and noise susceptibility. Hillocks and whiskers can cause short circuits to neighboring wires. EM is increasingly a signal wire issue as well. Wire self-heat (Joule heating) occurs when the dynamic current density is too high, resulting in EM.

6 Digital-analog integration
Approximately 50% of SoCs at 0.13 micron include critical analog/mixed-signal circuitry, and the percentage will increase in nanometer design. Making these sophisticated analog functions work at all, much less while sharing a chip with a number of large digital systems, is a huge design challenge. Although the analog circuitry often accounts for only a small percent of the transistors, it accounts for 20 percent of the area, 40 percent of the design effort, and 50 percent of the respins. Nanometer digital/mixed-signal (D/MS) designs require new design approaches to optimize the chip's overall performance and its yield. For more information regarding digital-analog convergence, see the Cadence Digital-Analog Convergence Executive Technology Brief.

7 Power consumption
Power consumption is an issue for a growing number of applications, from prolonging battery life in mobile equipment to minimizing package costs and cooling noise in stationary applications. Concerns with power consumption, and the concomitant implications for temperature and reliability, lead to multivoltage ICs. Other power-related issues include clocking structure design and leakage current, which increase the risk of signal integrity issues and place additional demands on ensuring electrical correctness. Since power consumption is directly related to wiring capacitance, power minimization requires careful wiring optimization and power distribution across the chip. Nanometer design tools must have the ability to cope with complex clocking schemes, multi-voltage blocks, and leakage minimization.

8 System signal transmission
Without effective IC packaging and timely design-in by system design teams, even the best silicon will fail in the market. High density pinouts require elaborate custom packaging, which can cost as much as the silicon itself. Ineffective chip I/O placement results can lead to silicon underutilization or even signals that are not routable. High frequency and sensitive analog/RF signals require careful, prioritized routing through the chip, package, and board. Analyzing system-level signal performance and integrity from die to die-through IC packages and across the board-is essential. Addressing system signal transmission issues is especially difficult since different design teams at different companies are often responsible for each element. For more information regarding system signal transmission, see the Cadence Silicon-Package-Board Convergence Executive Technology Brief.

9 Manufacturing rules
Manufacturing processes using copper wiring, chemical-mechanical polishing (CMP), and subwavelength lithography lead to exceedingly complex and arcane design rules. Antenna rules, for example, require careful handling to avoid via proliferation and to minimize wire lengths. In order to minimize ramp-up time, foundries continue to change the rules until long after the introduction of a new process, and the situation is worsening with each new process node. Nanometer routers must explicitly provide for variable width and variable spacing and must be capable of adapting to the requirements of copper wires, multiple vias, optical proximity correction (OPC), phase-shift masks (PSM), and CMP processes.

10 Yield optimization
More than 50% of SoCs end up in high-volume applications. As processes get smaller, process variability grows. Designing for the "worst case" becomes impractically conservative, and design-centering techniques must replace the use of process corners. At nanometer levels, intra-chip variances raise a whole new level of issues. Exotic nanometer process requirements and increasingly intractable optical lithography challenges make yield management a major design issue, not simply a manufacturing issue.

Lavi Lev is executive vice president and general manager for IC solutions at Cadence Design Systems. Before joining Cadence, Lavi was Senior Vice President of Engineering at MIPS Technologies. He has also led engineering teams at Silicon Graphics, MicroUnity Systems, Sun Microsystems, Intel Corporation, and National Semiconductor. With 20 years experience in the semiconductor industry and over 15 patents, Lavi has developed microprocessor and system-on-a-chip solutions for supercomputers, workstations, PCs, and consumer devices. He holds a bachelor of science degree in electrical engineering from Technion, Israel Institute of Technology.

Ping Chao is senior vice president and general manager for digital IC solutions at Cadence Design Systems. Ping is a co-founder of Cadence and has an extensive career in the EDA industry and electronic design. He founded and held executive management positions in three successful EDA start-up companies-ECAD, PiE Design Systems and Silicon Perspective-taking them through IPOs/acquisitions and growth to market leadership positions. He earned a B.S.E.E. degree from National Chiao-Tung University, Taiwan, and a M.S.E.E./C.S. degree from the University of California, Berkeley.