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eeDesign is the comprehensive source of information for electronics design tools and methodologies. Its scope includes EDA tools, silicon intellectual property (IP), chip design methodologies, and chip and system architectures. Your feedback is welcome.


  eeDesign Exclusives
Practical Power Network Synthesis For Power-Gating Designs
The article describes a method for properly sizing sleep transistors in power network synthesis. It introduces the concept of a "fake via" to enable power network synthesis using existing EDA tools.More »

  Headlines for Friday Nov 21, 2008
Business
  • IBM set to buy Transistive; keeps mum on price


      Headlines for Thursday Nov 20, 2008
    Business
  • Qimonda reportedly seeks ITC probe of Seagate, LSI
  • Aviza posts loss
  • ARM works with design houses to ease adoption
    Technology
  • ARM works with design houses to ease adoption


      Headlines for Wednesday Nov 19, 2008
    Business
  • Updated: Mentor's loss wider than anticipated
  • Analog Profile: John Nisbet
    Technology
  • New modeling technology said to reduce library data size
  • UoI gives sneak peak on multicore programming ideas
    Products
  • Micrel, Zilog to partner on subsystem-level modules
  • After iPhone, consumers seek handsome gadgets
  • ARC sounds out SoC designers looking for better bass
  • Agilent offers IP for mobile devices


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      Design Resources
    Designing for a dual Galileo-based GPS system
    Malcolm Lomer of SiGe Semiconductor discusses GPS design challenges with the Galileo satellite system.
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