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eeDesign is the comprehensive source of information for electronics design tools and methodologies. Its scope includes EDA tools, silicon intellectual property (IP), chip design methodologies, and chip and system architectures. Your feedback is welcome.


  eeDesign Exclusives
Practical Power Network Synthesis For Power-Gating Designs
The article describes a method for properly sizing sleep transistors in power network synthesis. It introduces the concept of a "fake via" to enable power network synthesis using existing EDA tools.More »

  Headlines for Thursday Dec 4, 2008
Products
  • Sun looks to extend Java's reach


      Headlines for Wednesday Dec 3, 2008
    Business
  • Analog Devices shutters DSP design center
  • Synopsys bucks trend, posts profit
  • Private chip companies shedding staff, too
  • Letter to the editor: Western engineers must 'sink or swim'
  • Firm claims win-win engagement for SIP vendors, customers
  • Thin micro-cell firm raises $13 million
  • Virage makes bid to buy LogicVision
  • Plurality offers 64-core processor as IP
  • Fate of Altis is uncertain, says Infineon
    Technology
  • AMS standard ready for review
  • Power.org release debug API specification
    Products
  • Groups team for Chinese PC TV reference designs
  • Cadence rolls multi-core design solution
  • Plurality offers 64-core processor as IP


      Headlines for Tuesday Dec 2, 2008
    Business
  • Panasonic, Samsung slip SiBeam some cash
    Products
  • Nokia takes on iPhone with its N97


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      Design Resources
    Designing for a dual Galileo-based GPS system
    Malcolm Lomer of SiGe Semiconductor discusses GPS design challenges with the Galileo satellite system.
    More »
     

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